Demand for display devices using electro-luminescence, light emitting diodes, plasma, fluorescent, liquid crystal and the like, for use in office equipment, computer and other display devices and other special-purpose display devices in increasing, due, in part to the fact that they can be produced to be thin.
Among such display devices, an AM-LCD using a thin film transistor (TFT) as a switch for a pixel element for a high-quality, high-resolution, low-power consuming display is being researched and developed widely today.
A poly-Si thin film transistor (poly-Si TFT), which uses poly-Si as a TFT channel layer for the AM-LCD device, provides high definition because of its high mobility when it is used for the pixel switching element. The poly-Si may also be used in driving circuits for controlling the pixel switching element. Poly-Si TFT can be formed on a peripheral area of a substrate simultaneously with the pixels (thereby forming integrated driving circuits on the LCD). Therefore using poly-Si TFT technology can reduce the cost of mounting drive chips and the size of the peripheral area.
Currently, available LCD integrated driving circuits are used in a small or medium size displays, such as, for example, 8 inch displays, which are generally used for projection type displays and viewfinders. The manufacturing process for them is the so-called high-temperature process, which has a solid phase semiconductor layer growing process (a process at about 600.degree. C.) or a heat oxide film growing process (a process at 900.degree. C. or higher) for forming the poly-Si TFT . Therefore, an expensive quartz substrate or highly heat-resistant substrate must be used.
However, if a low-temperature process, such as that which has been adopted for an amorphous silicon (a-Si) TFT-LCD and which has steps at a temperature of 600 or 450.degree. C. or below, can form a poly-Si TFT, a gate oxide film and a dopant activated area, which have the same characters as those formed by the high-temperature process, a glass substrate may be used. A plurality of LCD panels can be formed on a single substrate (yield of multiple LCD panels) by using a low cost large area glass substrate. Therefore, substantial benefits related to cost reduction and improvement of throughput can be expected.
An a-Si thin film crystallizing technology and a dopant activating technology using excimer laser annealing (ELA) are known in the low-temperature process. When the ELA is applied, the thermal damage to the substrate is decreased. Because the a-Si thin film is instantaneously melted and crystallized, a low-cost large glass substrate can be used.
FIG. 12 schematically shows a sectional view of the structure of a conventional poly-Si TFT. A channel 12 of a high resistant semiconductor layer formed of a poly-Si thin film is disposed on a transparent insulator film 11 that is disposed on a transparent substrate 10. The high resistant semiconductor layer 12 is formed by the following steps: depositing a hydrogenated amorphous silicon layer (a-Si:H layer) at a thickness of about, for example, 50 nm to about 70 nm using, for example, a conventional plasma chemical vapor deposition (CVD) method; dehydrogenating by heat annealing; and polycrystallizing by irradiating with an excimer laser. Low resistant semiconductor layers which makeup a source 13 and a drain 14 region are formed next to the high resistant semiconductor layer 12, which is the TFT channel section. The low resistant semiconductor layers 13, 14 are activated by annealing after doping impurities such as phosphorus or boron.
A gate insulator 16 is formed at a thickness of about 70 nm to about 100 nm on the channel 12. This gate insulator 16 is formed using atmosphere pressure CVD (APCVD), plasma enhanced CVD (PE-CVD) or electron cyclotron resonance PECVD (ECR-PECVD). A gate 18 is formed on the gate insulator 16. An insulator 21 is formed on the source 13, the drain 14 and the gate insulator 16. A source electrode 19 and a drain electrode 20 are connected to the low resistant semiconductor source and drain 13, 14 respectively, between the gate 18 and the source electrode 19 or the drain electrode 20. The gate 18 is required to have some thickness due to the following reasons:
a) The gate 18 works as a mask when the impurity is implanted to the source and the drain regions 13, 14 to decrease the parasitic capacitance of the device. If the gate 18 does not have an appropriate thickness, the dopant is implanted into both the gate insulator 16 and the channel 12, and the device characteristics are deteriorated. In other words, the voltage resistance of the gate is lowered, or a threshold voltage (Vth) is shifted. PA1 b) If the same material is used, a line resistance decreases as the layer thickness increases. Therefore, the gate layer must have an appropriate thickness in view of countermeasure against the delay of the gate pulse. PA1 a) When the gate electrode is a thick layer and its end face is fabricated to be perpendicular with the substrate surface, a coverage failure is caused in the insulator, resulting in lowering the yield (FIG. 12). PA1 b) When the gate electrode is shaped to have a tapered end face to decrease the occurrence of a coverage failure, a defective region is left in a part of a channel below the end face of the gate electrode due to insufficient activation, resulting in deteriorating the device characteristics (FIG. 13, FIG. 14).
The inventors of the present invention have found that the gate thickness must preferably be in the range of 250 nm to 350 nm or more if the gate electrode is made of a Mo--Ta alloy.
It has been experimentally found that a coverage failure 51 tends to result in the insulator 21 on the gate 18, as shown in FIG. 12, when the gate 18 has a thickness of about 250 nm to about 350 nm and a cross section (a side view intersecting the direction of the gate length) having a vertical wall to the substrate surface. Accordingly, it is difficult to manufacture the TFT structure without the failure 51. The coverage failure 51 causes a lower yield.
To prevent the problem of coverage failure, the gate 18 is formed to have a tapered wall as shown in FIG. 13. When the gate 18 has a tapered wall, the occurrence of coverage failure is reduced. However, forming a gate having a tapered wall includes other disadvantages as described below.
The gate 18 functions as the mask to implant the dopant to the source and the drain regions 13, 14. When the gate electrode has a tapered end face, as shown in FIG. 14, the dopant is also implanted to a part 52 in the channel 12 below the edge of the gate 18 corresponding to the taper shape.
When the glass substrate is used in the low temperature process, heat annealing at 600.degree. C. or higher cannot be adopted because the glass substrate cannot resist the heat anneal step. Therefore, an energy beam annealing method, such as the ELA, is used in the activating step of the low temperature process. However, because the energy beam is reflected on the gate surface and does not reach the part 52 below the tapered end in which the dopant is implanted, the part 52 is left inactivated. Therefore, energy beam annealing cannot be used as an activating step in the conventional manner when the gate electrode has its end face tapered in the poly-Si TFT.
Accordingly, conventional poly-Si TFT producing processes have the following problems and corresponding disadvantages: